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authorSimon South <simon@simonsouth.net>2023-02-10 08:16:55 -0500
committerChristopher Baines <mail@cbaines.net>2023-02-11 20:34:22 +0000
commit8553148dfb91a9957b95c7bc6bc108cc0a973f9e (patch)
tree99aa0da39656d06848443df6c9dcc2b0e95d0b8e /gnu/packages/fpga.scm
parentade3bfd0361bfd62ef8faef6eb1ae9f776f6148b (diff)
downloadguix-8553148dfb91a9957b95c7bc6bc108cc0a973f9e.tar
guix-8553148dfb91a9957b95c7bc6bc108cc0a973f9e.tar.gz
gnu: yosys: Update to 0.26.
* gnu/packages/fpga.scm (yosys): Update to 0.26. [source]: Disable unnecessary recursive checkout. [arguments]<#:phases>: Expand "fix-paths" phase to match new version; remove obsolete "fix-iverilog-references" phase; add wrap phase. [inputs]: Add gtkwave, zlib, python, python-click. Signed-off-by: Christopher Baines <mail@cbaines.net>
Diffstat (limited to 'gnu/packages/fpga.scm')
-rw-r--r--gnu/packages/fpga.scm47
1 files changed, 19 insertions, 28 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 4a01714e81..cc7420f37f 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -137,16 +137,15 @@ For synthesis, the compiler generates netlists in the desired format.")
(define-public yosys
(package
(name "yosys")
- (version "0.9")
+ (version "0.26")
(source (origin
(method git-fetch)
(uri (git-reference
(url "https://github.com/YosysHQ/yosys")
- (commit (string-append "yosys-" version))
- (recursive? #t))) ; for the ‘iverilog’ submodule
+ (commit (string-append "yosys-" version))))
(sha256
- (base32
- "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
+ (base32
+ "0s79ljgbcfkm7l9km7dcvlz4mnx38nbyxppscvh5il5lw07n45gx"))
(file-name (git-file-name name version))))
(build-system gnu-build-system)
(arguments
@@ -162,7 +161,11 @@ For synthesis, the compiler generates netlists in the desired format.")
(substitute* "./backends/smt2/smtio.py"
(("\\['z3")
(string-append "['" (search-input-file inputs "/bin/z3"))))
- (substitute* "./passes/cmds/show.cc"
+ (substitute* "./kernel/fstdata.cc"
+ (("vcd2fst")
+ (search-input-file inputs "/bin/vcd2fst")))
+ (substitute* '("./passes/cmds/show.cc"
+ "./passes/cmds/viz.cc")
(("exec xdot")
(string-append "exec " (search-input-file inputs
"/bin/xdot")))
@@ -179,26 +182,6 @@ For synthesis, the compiler generates netlists in the desired format.")
(("ABCEXTERNAL \\?=")
(string-append "ABCEXTERNAL = "
(search-input-file inputs "/bin/abc"))))))
- (add-before 'check 'fix-iverilog-references
- (lambda* (#:key inputs native-inputs #:allow-other-keys)
- (let ((iverilog (search-input-file (or native-inputs inputs)
- "/bin/iverilog")))
- (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
- "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
- "./techlibs/ice40/tests/test_bram.sh"
- "./techlibs/ice40/tests/test_ffs.sh"
- "./techlibs/xilinx/tests/bram1.sh"
- "./techlibs/xilinx/tests/bram2.sh"
- "./tests/bram/run-single.sh"
- "./tests/realmath/run-test.sh"
- "./tests/simple/run-test.sh"
- "./tests/techmap/mem_simple_4x1_runtest.sh"
- "./tests/tools/autotest.sh"
- "./tests/vloghtb/common.sh")
- (("if ! which iverilog") "if ! true")
- (("iverilog ") (string-append iverilog " "))
- (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
- iverilog "\""))))))
(add-after 'install 'add-symbolic-link
(lambda* (#:key inputs #:allow-other-keys)
;; Previously this package provided a copy of the "abc"
@@ -206,7 +189,11 @@ For synthesis, the compiler generates netlists in the desired format.")
;; symbolic link so any external uses of that name continue to
;; work.
(symlink (search-input-file inputs "/bin/abc")
- (string-append #$output "/bin/yosys-abc")))))))
+ (string-append #$output "/bin/yosys-abc"))))
+ (add-after 'install 'wrap
+ (lambda* (#:key inputs #:allow-other-keys)
+ (wrap-program (string-append #$output "/bin/yosys-witness")
+ `("GUIX_PYTHONPATH" ":" prefix (,(getenv "GUIX_PYTHONPATH")))))))))
(native-inputs
(list bison
flex
@@ -218,12 +205,16 @@ For synthesis, the compiler generates netlists in the desired format.")
(inputs
(list abc
graphviz
+ gtkwave
libffi
psmisc
readline
tcl
xdot
- z3))
+ z3
+ zlib
+ python
+ python-click))
(home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
(description "Yosys synthesizes Verilog-2005.")