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authorCayetano Santos <csantosb@inventati.org>2024-10-24 16:26:55 +0200
committerZheng Junjie <zhengjunjie@iscas.ac.cn>2024-10-31 14:12:02 +0800
commit9fb7333fc9482ff5435bc48f041b398b28d60d21 (patch)
tree9e00ee6986975bfaf64bb0a29cf9e0bcd5e862fa
parent3eb531f04ea21501722934b501e02e126431a079 (diff)
downloadguix-9fb7333fc9482ff5435bc48f041b398b28d60d21.tar
guix-9fb7333fc9482ff5435bc48f041b398b28d60d21.tar.gz
gnu: openfpgaloader: Update to 0.12.1.
* gnu/packages/fpga.scm (openfpgaloader): Update to 0.12.1. [source]: Update url. Use GIT-FILE-NAME. [inputs]: Add eudev and libgpiod. [home-page]: Update it. Change-Id: Iae97a45364bff1b668ccab8de44a11a29d9284dd
-rw-r--r--gnu/packages/fpga.scm20
1 files changed, 12 insertions, 8 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 545ec3482d..c812ed3b7e 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -603,25 +603,29 @@ hardware designs in Verilog.")
(define-public openfpgaloader
(package
(name "openfpgaloader")
- (version "0.9.0")
+ (version "0.12.1")
(source (origin
(method git-fetch)
(uri (git-reference
- (url "https://github.com/trabucayre/openFPGALoader.git")
- (commit (string-append "v" version))))
- (file-name (string-append name "-" version "-checkout"))
+ (url "https://github.com/trabucayre/openfpgaloader")
+ (commit (string-append "v" version))))
+ (file-name (git-file-name name version))
(sha256
(base32
- "1v3bwzhsrnsn304cqhd5azn68cl847qv8w8cb8bl7372jiqz5wqq"))))
+ "0r4dxryhfa1brhyh4z5ixmr7bvcqf3p8b339k6vrmmqnwy497548"))))
(build-system cmake-build-system)
(native-inputs
(list pkg-config))
- (inputs
- (list libftdi libusb hidapi zlib))
+ (inputs (list eudev
+ hidapi
+ libftdi
+ libgpiod
+ libusb
+ zlib))
(arguments
`(#:tests? #f)) ; No tests exist
(synopsis "Utility for programming FPGA")
(description "This package provides a program to transfer a bitstream
to an FPGA.")
- (home-page "https://f4pga.org/")
+ (home-page "https://trabucayre.github.io/openFPGALoader")
(license license:asl2.0)))