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authorLudovic Courtès <ludo@gnu.org>2016-09-09 15:22:45 +0200
committerLudovic Courtès <ludo@gnu.org>2016-09-12 18:20:50 +0200
commite7e43727ce7b3426a31b2f50b035a5b0aba61d52 (patch)
tree6fda0b61a2832e7a545c206259f2ba4eca90f726 /gnu/packages/patches
parent24f2334e367e6218617f21e3abb287b211a1dcd1 (diff)
downloadguix-e7e43727ce7b3426a31b2f50b035a5b0aba61d52.tar
guix-e7e43727ce7b3426a31b2f50b035a5b0aba61d52.tar.gz
gnu: gcc: Work around ARM bootstrapping failure (GCC bug #71399).
* gnu/packages/patches/gcc-arm-bug-71399.patch: New file. * gnu/local.mk (dist_patch_DATA): Add it. * gnu/packages/gcc.scm (gcc-4.9)[source]: Use it.
Diffstat (limited to 'gnu/packages/patches')
-rw-r--r--gnu/packages/patches/gcc-arm-bug-71399.patch55
1 files changed, 55 insertions, 0 deletions
diff --git a/gnu/packages/patches/gcc-arm-bug-71399.patch b/gnu/packages/patches/gcc-arm-bug-71399.patch
new file mode 100644
index 0000000000..6f04fece0e
--- /dev/null
+++ b/gnu/packages/patches/gcc-arm-bug-71399.patch
@@ -0,0 +1,55 @@
+Revert the following commit to work around a bootstrap comparison failure on
+ARMv7, as reported at <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71399>.
+
+commit f6ab85b7049a03962ea98924d00802da357a1ad3
+Author: renlin <renlin@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Wed Dec 2 14:06:31 2015 +0000
+
+ [PR67383][ARM][4.9]Backport of "Allow any register for DImode values in Thumb2"
+
+ This partially fix PR67383. It allows the reload more flexibility to choose
+ spilling pseudo registers.
+
+
+ gcc/ChangeLog:
+
+ 2015-12-02 Renlin Li <renlin.li@arm.com>
+
+ Backport from mainline.
+ 2014-04-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/arm/arm.c (arm_hard_regno_mode_ok): Loosen
+ restrictions on core registers for DImode values in Thumb2.
+
+
+ git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@231177 138bc75d-0d04-0410-961f-82ee72b054a4
+
+diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
+index 8ba6060..d9028a1 100644
+--- b/gcc/config/arm/arm.c
++++ a/gcc/config/arm/arm.c
+@@ -22624,19 +22624,12 @@
+ }
+
+ /* We allow almost any value to be stored in the general registers.
+- Restrict doubleword quantities to even register pairs in ARM state
+- so that we can use ldrd. Do not allow very large Neon structure
+- opaque modes in general registers; they would use too many. */
++ Restrict doubleword quantities to even register pairs so that we can
++ use ldrd. Do not allow very large Neon structure opaque modes in
++ general registers; they would use too many. */
+ if (regno <= LAST_ARM_REGNUM)
+- {
+- if (ARM_NUM_REGS (mode) > 4)
+- return FALSE;
+-
+- if (TARGET_THUMB2)
+- return TRUE;
+-
+- return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
+- }
++ return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0)
++ && ARM_NUM_REGS (mode) <= 4;
+
+ if (regno == FRAME_POINTER_REGNUM
+ || regno == ARG_POINTER_REGNUM)