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| author | Tobias Geerinckx-Rice <me@tobias.gr> | 2018-02-19 05:41:37 +0100 |
|---|---|---|
| committer | Tobias Geerinckx-Rice <me@tobias.gr> | 2018-02-19 06:00:33 +0100 |
| commit | 77659ff3ad58c779209737dfd542cf4d6ecc057e (patch) | |
| tree | 130b5e122f6c9110f85f1cc1b55c0ee4af78b1c0 | |
| parent | c046904d7470027f2666d5ba652d8385f719c779 (diff) | |
| download | patches-77659ff3ad58c779209737dfd542cf4d6ecc057e.tar patches-77659ff3ad58c779209737dfd542cf4d6ecc057e.tar.gz | |
gnu: iverilog: Use Texinfo in description.
* gnu/packages/fpga.scm (iverilog)[description]: Substitute @command for
inverted commas.
| -rw-r--r-- | gnu/packages/fpga.scm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index 0144b01f5d..60c5f96a87 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -105,7 +105,7 @@ It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. -This intermediate form is executed by the ``vvp'' command. +This intermediate form is executed by @command{vvp}. For synthesis, the compiler generates netlists in the desired format.") ;; GPL2 only because of: ;; - ./driver/iverilog.man.in |