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author | Danny Milosavljevic <dannym@scratchpost.org> | 2019-01-15 14:41:21 +0100 |
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committer | Danny Milosavljevic <dannym@scratchpost.org> | 2019-01-15 16:46:45 +0100 |
commit | 9210a6c082cb201b46aa50eea9aecc4334ead83a (patch) | |
tree | 0c37cdc07c51278df720a5f66d75027956f9938b | |
parent | eccd3f6d2ef09fcfccf5e4e09be13b79089c60d1 (diff) | |
download | patches-9210a6c082cb201b46aa50eea9aecc4334ead83a.tar patches-9210a6c082cb201b46aa50eea9aecc4334ead83a.tar.gz |
gnu: yosys: Update to 0.8.
* gnu/packages/fpga.scm (yosys): Update to 0.8.
-rw-r--r-- | gnu/packages/fpga.scm | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index 46edda02d2..f6bb3280f0 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -120,7 +120,7 @@ For synthesis, the compiler generates netlists in the desired format.") (define-public yosys (package (name "yosys") - (version "0.7") + (version "0.8") (source (origin (method git-fetch) (uri (git-reference @@ -129,7 +129,7 @@ For synthesis, the compiler generates netlists in the desired format.") (recursive? #t))) ; for the ‘iverilog’ submodule (sha256 (base32 - "1ssrpgw0j9qlm52g1hsbb9fsww4vnwi0l7zvvky7a8w7wamddky0")) + "1qwbp8gynlklawzvpa4gdn2x0hs8zln0s3kxjqkhfcjfxffdcpvv")) (file-name (git-file-name name version)) (modules '((guix build utils))) (snippet |