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authorSimon South <simon@simonsouth.net>2020-06-01 13:15:32 -0400
committerEfraim Flashner <efraim@flashner.co.il>2020-06-28 10:45:59 +0300
commit2995be77e1f81ca3d90f18e0e819952ea02003ad (patch)
tree37d11efcb3a96fb2401fb0a49a6ca06e78ba463d /gnu/packages/patches/jamvm-2.0.0-opcode-guard.patch
parent6c9dca5a9bc3aeab260bc125e8ddc08a5107ec4e (diff)
downloadguix-2995be77e1f81ca3d90f18e0e819952ea02003ad.tar
guix-2995be77e1f81ca3d90f18e0e819952ea02003ad.tar.gz
gnu: jamvm: Add aarch64-linux support.
* gnu/packages/java.scm (classpath-devel)[source]: Add (existing) patch. (jamvm)[source]: Add patches. [arguments]: Inherit non-overridden arguments (particularly #:phases) from jamvm-1-bootstrap. * gnu/packages/patches/jamvm-2.0.0-aarch64-support.patch: New file. * gnu/packages/patches/jamvm-2.0.0-opcode-guard.patch: New file. * gnu/local.mk (dist_patch_DATA): Add files. Signed-off-by: Efraim Flashner <efraim@flashner.co.il>
Diffstat (limited to 'gnu/packages/patches/jamvm-2.0.0-opcode-guard.patch')
-rw-r--r--gnu/packages/patches/jamvm-2.0.0-opcode-guard.patch35
1 files changed, 35 insertions, 0 deletions
diff --git a/gnu/packages/patches/jamvm-2.0.0-opcode-guard.patch b/gnu/packages/patches/jamvm-2.0.0-opcode-guard.patch
new file mode 100644
index 0000000000..5415c27a62
--- /dev/null
+++ b/gnu/packages/patches/jamvm-2.0.0-opcode-guard.patch
@@ -0,0 +1,35 @@
+From ca11b53896365c948426974cb90e8f71c70d123b Mon Sep 17 00:00:00 2001
+From: Simon South <simon@simonsouth.net>
+Date: Sun, 31 May 2020 20:36:43 -0400
+Subject: [PATCH] Guard floating-point opcodes with explicit memory barrier
+
+---
+ src/interp/engine/interp-inlining.h | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/src/interp/engine/interp-inlining.h b/src/interp/engine/interp-inlining.h
+index 3339b0e..4ee5c5a 100644
+--- a/src/interp/engine/interp-inlining.h
++++ b/src/interp/engine/interp-inlining.h
+@@ -78,8 +78,17 @@
+ 4.3, we need to insert a label, and ensure its address
+ is taken (to stop it being optimised out). However,
+ this reduces performance on PowerPC by approx 1 - 2%.
++
++ With gcc 5 and newer an asm statement with a "memory"
++ clobber argument explicitly sets a memory barrier for the
++ compiler, preventing it from reordering memory accesses
++ in a way that breaks decaching.
+ */
+-#if (__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)
++#if (__GNUC__ > 4)
++#define DEF_GUARD_TABLE(level) /* none */
++#define GUARD(opcode, level) __asm__("" ::: "memory");
++#define GUARD_TBLS /* none */
++#elif (__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)
+ #define DEF_GUARD_TABLE(level) DEF_HANDLER_TABLE(level, GUARD)
+ #define GUARD(opcode, level) label(opcode, level, GUARD)
+ #define GUARD_TBLS , HNDLR_TBLS(GUARD)
+--
+2.26.2
+